1. Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the formation of terminal metal layers and bonding pads.
2. Background of the Invention and Description of Prior Art
Integrated circuits are manufactured by forming discrete semiconductor devices in the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices, contacting their active elements, and wiring them together to create the desired circuits. The wiring layers are formed by depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into the openings. A conductive layer is applied over the insulating layer and patterned to form wiring interconnections between the device contacts, thereby creating a first level of basic circuitry. The circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with conductive via pass throughs.
Depending upon the complexity of the overall integrated circuit, several levels of wiring interconnections are used. On the uppermost level the wiring is terminated at metal pads to which the chip""s external wiring connections are bonded. These bonding pads are generally large in size compared to the interconnection wiring lines, typically measuring larger than about 50xc3x9750 microns.
A method for forming the uppermost or top interconnection layer is the damascene process, whereby openings and trenches, comprising an image of the interconnection pattern are formed in an insulative layer. A metal layer is then deposited into the openings and over the insulative layer. Finally, the metal is polished back to the insulative layer leaving the metal pattern inlaid within the insulative layer. Polishing back of the metal layer is accomplished by CMP (chemical mechanical polishing), a relatively old process which has found new application in planarization of insulative layers and more recently in the damascene process. In a single damascene process a metal line pattern is generated which connects to subjacent vias or contacts. In a dual damascene process, both vias and contacts and an interconnection stripe pattern are formed by a single metal deposition and CMP. A description of both single and dual damascene processes may be found in Chang, C. Y. and Sze, S. M., xe2x80x9cULSI Technologyxe2x80x9d McGraw-Hill, New York, (1996), p444-445 and in El-Kareh, B., xe2x80x9cFundamentals of Semiconductor Processing Technologiesxe2x80x9d, Kluwer, Boston(1995), p563-4.
Carey, et.al., U.S. Pat. No. 5,219,787 shows a method for forming vias and wiring lines in a polyimide base by first forming a trench and via pattern in polyimide layers, depositing a copper seed layer, and then plating copper. The copper is polished back to the polyimide leaving metallization in the trenches and vias. Matsuura, U.S. Pat. No. 5,598,027 cites a metal deposition/polish back (damascene) method for forming interconnection layers using dry etching to form grooves in the insulating layers. After the interconnection material is deposited, the surface is polished back by CMP leaving the conductive pattern in the grooves.
The metal wiring layers, typically of an aluminum alloy or of an aluminum alloy containing copper and silicon, are deposited by sputtering or by vacuum evaporation. In the damascene process, copper metallization may also be used. The final metal interconnection layer includes the bonding pads which are typically located in the periphery of the integrated circuit. When large area features, such as bonding pads, are included in a damascene processed wiring pattern, a problem of bonding pad dishing arises when the metal is polished back to the insulative layer. Referring to FIG. 1 there is shown a planar view of a portion of the top metallization level of an integrated circuit on a wafer 20. A bonding pad 24 and wiring lines 26 lie embedded in an insulating layer 22. FIG. 1 is not drawn to scale the pad 24 is of the order of 50 by 50 microns square or larger and the wiring lines 26 are only of the order one micron or less in breadth.
A cross section of the region on wafer 20 indicated by the line 2-2xe2x80x2 is shown in FIG. 2A at the point in the process after a metal layer 25 has been deposited onto the patterned insulative layer 22. The wide portion of metal 24 in the insulator is to become a bonding pad. When the substrate wafer is polished by CMP, the surfaces of the wide metal bonding pads tend to become dished as illustrated by the curvature 28 in FIG. 2B.
The dishing weakens the pad, by creating a thin central region. A subsequently attached wire bond will not only be weak mechanically, but also excessively resistive. A passivation layer 29 is applied over the layer 22 and the metal pattern. The passivation layer 29 seals the interconnection metallization on the wafer from contaminants and moisture, and also serves as a scratch protection layer. The passivation layer 29 typically consists of a layer of silicon nitride or a composite layer of phosphosilicate glass (PSG) over silicon oxide. The layer 29 is deposited by plasma enhanced chemical vapor deposition (PECVD). An opening 28 to the bonding pad is patterned and etched in the passivation layer 29 by a plasma etching process.
Weakening of the bonding pad caused by the CMP dishing is reflected by high yield losses at wafer acceptance testing(WAT) and at subsequent package stress testing. These yield losses also forewarn a reliability degradation. Dummy pads are sometimes added on the interconnection level to counteract CMP dishing. These pads are sacrificial and are not connected to interconnection lines. This awkward fix also lowers the integrity of the interconnection lines.
An alternative method for forming the top interconnection layer, including the bonding pads is to deposit and pattern the metal layer on the un-patterned surface of the insulative layer 22. The passivation layer is then deposited over the metal pattern. This is an older method, a predecessor of the damascene method, and is not favorably compatible with current high density multilevel interconnection technology because it produces a higher resistance, and higher defect densities.
Accordingly, it is an object of this invention to provide a method for forming a top interconnection level of a multilevel integrated circuit including bonding pads.
It is another object of this invention to provide a method for forming a top interconnection level of a multilevel integrated circuit by a damascene process with bonding pads formed by an etch process.
It is yet another object of this invention to provide a method for forming a top interconnection level of a multilevel integrated circuit including conductive base segments for bonding pads by a damascene process.
It is still another object of this invention to provide a method for forming a top interconnection level of a multilevel integrated circuit wherein the bonding pads connected to the level are elevated above the level thereby reducing the impact of environmental or other external electrical disturbances on the interconnection level.
It is yet another object of this invention to provide a method for forming a top interconnection level of a multilevel integrated circuit without the occurrence of dishing of the bonding pads.
It is yet another object of this invention to eliminate the need for dummy bonding pads on a top interconnection level of a multilevel integrated circuit.
These objects are accomplished by first forming the necessary wiring channels of the top interconnection level by patterning trenches and vias in an insulative layer. Bonding pads are not patterned in this insulative layer but segments of interconnection lines which form bases for connecting bonding pads are included. The base segments may be simple terminations of the interconnection wiring or they may be oversized terminations having dimensions somewhat larger than the interconnection line width but much smaller than those of the bonding pads. The interconnection metallurgy is then deposited. In a first embodiment, the interconnection metallurgy is polished back to the insulative layer surface by CMP and a second metal layer is deposited. Bonding pads are then patterned in the second metal layer by plasma etching.
In a second embodiment, the deposited interconnection metallurgy is partially polished back by CMP to planarize the surface. Bonding pads are then patterned on the residual conductive layer and the layer is etched back to the insulative layer surface, leaving the bonding pads on the surface of the insulative layer, connected to the subjacent wiring level through the access openings. This method is limited to metallurgies which lend themselves to dry plasma etching such as aluminum, aluminum alloys, and tungsten. The bonding pads may then be formed of another metal such as aluminum or tungsten. An advantage of both embodiments is that the thickness of the bonding pads is independent of the thickness of the interconnection level.
A passivation layer is deposited over the exposed top interconnection level and bonding pads and patterned to form openings over the bonding pads. Bonding pads formed by the methods of the embodiments are robust and flat. Because the bonding pads lie above the top interconnection level the risk of wire bonding damage to the interconnection level is diminished.